1. Field of the Invention
The present invention relates to a thin film transistor (TFT), a method of fabricating the same and a flat panel display using the TFT. More particularly, the invention relates to a TFT having a gate overlapped lightly doped drain (GOLDD) structure, a method of fabricating the same and a flat panel display using the TFT.
2. Description of the Related Art
An active-matrix flat panel display can use a TFT as a switching element. TFTs may be used, for example, as pixel-driving TFTs formed in each pixel and driving the pixels, and as driving-circuit TFTs driving the pixel-driving TFTs and transmitting a signal to a scan line (gate line) and a signal line (data line).
Among various TFTs, a polycrystalline silicon TFT can be fabricated at a temperature similar to that for fabricating an amorphous silicon TFT due to technological advances. In particular the advance of crystallization technology using lasers may permit this relatively low temperature fabrication of TFTs. Polycrystalline silicon may allow electrons or holes to have high mobility as compared with amorphous silicon in a TFT. It thus may be possible to realize an improved complementary metal-oxide semiconductor (CMOS) TFT having n- and p-channels. Accordingly, polycrystalline silicon can be used to form pixel-driving TFTs and driving-circuit TFTs on large-sized insulating substrates.
In a polycrystalline silicon CMOS TFT, an n-channel metal oxide semiconductor (NMOS) TFT generally uses phosphorus (P) as a dopant. Phosphorus (P) has an atomic weight greater than boron (B): the dopant generally used in a p-channel metal oxide semiconductor (PMOS) TFT. One reason for this choice is so that a silicon crystal lattice thereof is less likely to become damaged at a predetermined region and remain unrecovered in a sequential activating process.
Such damaged region decreases the mobility of electrons. This decrease in electron flow into a gate insulating film or a metal-oxide semiconductor (MOS) interface, when the electron is accelerated from a source region to a drain region, is called hot carrier stress. Therefore, the damaged region may have a deleterious effect on circuit operation of the flat display panel, and may increase the off-current.
To solve the foregoing problems, various structures such as an off-set structure, a lightly doped drain (LDD) structure, and the like have been proposed. In the case of the off-set structure, an off-set region may be provided to form an imperfect doping region on a predetermined region between the gate and the source/drain regions, so that an electric field applied to a junction area is reduced by great resistance due to the off-set region, thereby decreasing the off-current. In the case of the LDD structure, an LDD is formed by lowering the doping concentration applied to a predetermined region between the source and drain regions, so that the off-current is decreased and the reduction of the on-current is minimized.
However, as low temperature poly silicon (LTPS) technology is highly integrated, the conventional off-set and LDD structures provide limited enhancement to the reliability of a short channel device. One way to overcome that limit may be to implement a thin film transistor with a gate overlapped lightly doped drain (GOLDD) structure.
FIGS. 1A, 1B, 1C, and 1D are cross-sectional views for illustrating a fabrication process of a conventional thin film transistor with a GOLDD structure.
As shown in FIG. 1A, a buffer layer 110 may be formed on an insulating substrate 100. Then an amorphous silicon film may be deposited on the buffer layer 110 and crystallized into a polycrystalline silicon film. Thereafter, an active layer 120 may be formed by patterning the polycrystalline silicon film.
After forming the active layer 120, a gate insulating film 130 may be formed on a substantial portion of an entire surface of the insulating substrate 100 formed with the active layer 120.
After forming the gate insulating film 130, a first photoresist pattern 140 may be formed for doping low-concentration impurities having a predetermined conductive type (i.e., for LDD doping).
After the first photoresist pattern 140 is formed, the low-concentration impurities may be doped using the first photoresist pattern 140 as a mask, so that low-concentration source/drain regions 123S, 123D may be formed on the active layer 120. A region between the low-concentration source/drain regions 123S and 123D may be used as a channel region 121 of the TFT.
As shown in FIG. 1B, after forming the low-concentration source/drain regions 123S, 123D on the active layer 120 through the light doping, the first photoresist pattern 140 may be removed, and a gate electrode material film 150 may be formed on the gate insulating film 130. Then, a second photoresist pattern 160 is formed for forming a gate electrode.
Here, the second photoresist pattern 160 is formed, partially overlapping with the low-concentration source/drain regions 123S and 123D. Further, the width of the overlapped region is limited to a minimum of about 0.5 μm or more depending on resolution of a stepper.
As shown in FIG. 1C, a gate electrode 155 may be formed by patterning the gate electrode material film 150 using the second photoresist pattern 160 as the mask. In this situation, the gate electrode 155 may be formed partially overlapping the respective low-concentration source/drain regions 123S and 123D due to the second photoresist pattern 160.
After forming the gate electrode 155 to overlap with the respective low-concentration source/drain regions 123S and 123D, high-concentration impurities may be doped onto the active layer 120 through the gate electrode 155 used as the mask, thereby forming high-concentration source/drain regions 125S and 125D.
As shown in FIG. 1D, an interlayer insulating film 170 having contact holes 171, 175 through which the high-concentration source/drain regions 125S, 125D are partially exposed is formed on the entire surface of the insulating substrate 100 with the gate electrode 155. Then, source/drain electrodes 181, 185 are formed to be electrically connected to the high-concentration source/drain regions 125S, 125D through the contact holes 171, 175, thereby finally forming a thin film transistor with the GOLDD structure.
However, in a conventional thin film transistor with GOLDD structure, it may be difficult to reduce the low-concentration source/drain regions overlapping with the gate electrode. That is, it may be difficult to reduce the width of an LDD range to about 0.5 μm or less because of the resolution of the stepper used in the fabrication process.
Further, in a conventional thin film transistor with GOLDD structure, the low-concentration impurities may be doped using a photoresist mask. Then, after the gate electrode is formed, high-concentration impurities may be doped. Thus, an additional mask is needed to dope the low-concentration impurities. Another problem that can occur is that the gate electrode can be defectively aligned.